Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

A practical reference for specifying timing requirements in integrated circuit design, this book explains how Synopsys Design Constraints (SDC) affect synthesis, static timing analysis, placement and routing. It connects the underlying concepts with command syntax and worked examples, helping engineers express design intent consistently throughout the implementation flow.
 
Coverage includes clocks, timing exceptions, input and output delays, electrical constraints and loads. The discussion addresses how to choose between commands that may produce similar timing effects, with attention to clarity, maintenance and reuse. Examples support both ASIC and FPGA design contexts.
 
Sridhar Gangadharan and Sanjay Churiwala draw on extensive experience in electronic design automation and VLSI engineering. Their explanations are aimed at practitioners who need to understand the consequences of their constraints as well as the syntax used to write them.
 
A focused guide for synthesis, timing analysis and implementation engineers, as well as students developing skills in digital hardware design. Add this copy to your engineering bookshelf for a detailed grounding in SDC and timing constraints.

• Encadernação: Capa mole
• Ano: 2013
• Páginas: 226
• ISBN: 978-1-4899-8916-1